Synthesis of regular VLSI layouts from high level descriptions

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dc.contributor.advisorPrasad, Surendra
dc.contributor.authorRamayya, Kumar
dc.date.accessioned1999-08-23
dc.date.accessioned2024-10-29T11:15:39Z
dc.date.issued1986
dc.identifier.urihttp://10.17.50.146:4000/handle/123456789/3047
dc.relation.ispartofseriesTH1523
dc.subjectMach.-Transformer Compon.
dc.titleSynthesis of regular VLSI layouts from high level descriptions
dc.typeThesis

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