Cmos scaling considerations in sub 10-nm node multiple-gate fets

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dc.contributor.advisorDixit, Abhisek
dc.contributor.authorBansal, Anil Kumar
dc.date.accessioned2019-02-13
dc.date.accessioned2024-10-29T11:17:13Z
dc.date.issued2019
dc.identifier.urihttp://10.17.50.146:4000/handle/123456789/3394
dc.relation.ispartofseriesTH5830
dc.subject10-nm technology node
dc.titleCmos scaling considerations in sub 10-nm node multiple-gate fets
dc.typeThesis

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